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The phase shifter was to be of the digital type with 4 bits of commandable phase shifts; this means, 24 = 16 phase-shift states. The insertion loss was to be smaller than what is achievable with conventional technology (e.g., smaller than 6.5 dB), which is approximately what is exhibited by a 4-bit Ka-band pseudomorphic high electron mobility transistor (pHEMT) MMIC phase shifter [22].

K-band covers the frequency range between 26.5 and 40 GHz, with a wavelength of l = c/ er_Si f = 3 ´ 108 m/s/ 119 . ´ 265 ´ 109Hz ´ 39.37 in/m = 0.129 in, at 26.5 GHz, assuming silicon er_Si = 11.9 implementation. Because of the small size afforded by this frequency range, the switched-line topology was adopted.

Circuit Design and Implementation:

The implementation of this phase shifter may be understood from an examination of Figures 5.5 and 5.6. In this implementation (Figure 5.5), 1-bit sections are utilized (Figure 5.6). Each section routes the incoming signal to one of two paths: through a reference line length, which produces a reference phase shift, or through a line with length equal to the reference line plus a length representing the desired phase shift.

The switches are implemented by shunt capacitively coupled MEM switches and their function is to connect/disconnect the main transmission line to quarter-wave open stubs. As indicated in Figure 5.6, the tip of the quarter-wave stubs is a half-wave away from the T-junction between the main line and the two paths. Under these circumstances, when switch S1 is on (down), the open at the tip of its quarter-wave stub is transformed to an open at the T-junction.

Therefore, the incoming signal is precluded from taking the short/reference path and, instead, propagates down the long path, which exceeds the reference length by the desired phase shift. This implements 1 bit. As shown in Figure 5.5, cascading four such sections, providing 180°, 90°, 45°, and 22.5°, results in the 4-bit phase shifter. The MEM switches are biased by a resistive bias network connected to the membranes via open stubs. Again, 10-kW resistors were utilized, which simultaneously provided DC/RF isolation without slowing down the switching time of the MEM switches. The MEM switches utilized [21] were of the CPW membrane type and exhibited on and off capacitances of 3 pF and 35 fF, respectively, actuation voltage of about 45V, and on/off switching times of about 3 to 6 ms. The circuit was implemented using microstrip transmission lines on 0.006-in-thick high-resistivity silicon.

No information was provided in [18] on metal thickness, but with a skin-depth of 0.46 mm at 26.5 GHz, conductors made of 2.5-mm-thick gold (sAu = 4.55 ´ 107 S/m) [20], (i.e., about five times the skin depth) would have been good enough. Upon observing, it is noticed that the control signal for each MEM switch is applied via resistors R, and that each MEM switch is in series with a 10-pF capacitor. The resistors were selected to have a value of 10 kW (i.e., large enough to serve as RF-dc decoupling elements), while the capacitors embody the dual role of RF shorts for terminating the delay line and blocking capacitors for isolating the control voltage from ground.