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The fundamental function of a phase shifter circuit is to produce a replica of the signal applied at its input, but with a modified phase. Its performance is characterized by its insertion loss, bandwidth, power dissipation, power handling capability, and insertion phase [12]. Depending on the nature of the insertion phase (i.e., whether switchable continuously or in discrete steps), phase shifters are further classified into analog and digital, respectively. In the analog phase shifter (Figure 5.1), the propagation properties of a transmission line, particularly its phase velocity [6],where Lt and Ct are the inductance and capacitance per unit length, respectively, are varied as a function of a control voltage. Thus, in a capacitively loaded line, as the shunt load capacitance increases, the phase velocity decreases with respect to that of the unloaded line, and it takes longer for the signal to travel a certain length of transmission line. As the loading capacitors CSwitch introduce a periodic load of period p on the line, the phase shifter exhibits a maximum frequency of operation given by which is the frequency at which reflections from all impedance discontinuities introduced by the load capacitors add coherently. Thus, there is a tradeoff among total line length, Bragg frequency, unloaded transmission line characteristic impedance, insertion loss, and number of switches used. One of the most recent examples of this approach is that of Barker and Rebeiz [13], who demonstrated a MEM switch-loaded 0 to 60 GHz true time delay (TTD) distributed phase shifter with 1.8-dB loss/84° at 40 GHz, and 2-dB loss/118° at 60 GHz.

One of the drawbacks of analog phase shifters is that they tend to be sensitive to noise in the control voltage line. In the digital phase shifter, the incoming input signal is routed/ switched through one of many alternate paths to the output, so as to introduce specific phase shifts with minimum loss. As shown there are four essential types of digital phase shifters: the switched line, the loaded line, the switched lowpass-/highpass-filter, and the reflection type phase shifters. The fundamental unit (1 bit) of the switched-line phase shifter is shown in Figure 5.2(a). Switches S1 and S2, and S3 and S4, are single-pole double-throw (SPDT) switches. By their proper activation, the incoming signal is routed either through the short-length path, via S1 and S3, or through long-length path, via S2 and S4, thus endowing it with commensurate delays.

The differential phase shift is given by Df = b(l – l ) long short (5.3) where b is the phase constant. In the loaded-line 1-bit unit , switchable stubs of characteristic impedance ZStub and electrical length qStub are separated by a spacing of line with length of q degrees (usually q = p/2) and characteristic impedance Z01, and disposed along a main transmission line of characteristic impedance Z0. Each stub is terminated in switches that enable a connection to ground depending on whether they are in the on or off state. For shunt stubs exhibiting susceptances BOPEN and BSHORT, the differential phase shift of the 1-bit unit is given by [14] The switched lowpass-/highpass-filter phase shifter unit [Figure 5.2(c)] exploits the phase shift displayed by dual lumped LC networks. Finally, the reflection-type phase shifter employs a hybrid whose output port is terminated in short-circuited transmission lines of electrical length q/2.

The state of the switches, whether open or closed, determines the phase of the wave coming from the out terminal with respect to that entering the in terminal. When the switches are open, the wave propagating down a transmission line of length q/2, picks up a phase shift of q/2 en route to the short-circuit termination, where it is reflected, and picks up another q/2 phase shift upon reaching the input to the line. Thus, a total phase shift of q is achieved. Clearly, this implementation tends to save space, compared to the switched-line topology. By proper selection of the total line length and by judicious location of the switches along it, various phase shifts may be obtained. This will become clearer in Section 5.2.2. For switches with normalized admittances in the open and closed states given by gOPEN + jbOPEN and gCLOSED + jbCLOSED, respectively, the differential phase shift is given by where G is the reflection coefficient in the open and closed switch states, respectively, given by [16] .

The motivation for using MEM switches is clear. Their negligible standby power consumption, activation power, and low insertion loss are superior to conventional semiconductor switches, thus enabling highperformance phase shifters. Recent examples of digital phase shifters are those demonstrated by Malczewsky et al. [17] and Pillans et al. [18] at X-band (8?10 GHz) and Ka-band (30?38 GHz), respectively. An examination of the various phase shifter approaches reveals the trade-offs confronted when deciding which one to choose for a given application. For example, when size minimization is a must, as in monolithic implementations with a small available area, it is clear that the switched-line and the loaded-line topologies are prohibitive, since they require line lengths commensurate with the wavelength of interest and, thus, tend to be large at low frequencies. Similarly, implementing the lowpass-/highpass-filter type in MMIC form requires large inductors, which are problematic to realize. Lastly, we have the reflection-type phase shifter, which while requiring a hybrid whose dimension is commensurate with the wavelength of interest and, thus, may be large at low frequencies, exhibits the wideband response properties of the hybrid and uses transmission lines that only need to be half the required phase-shift length.