Circuit Design and Implementation
Based Circuit DesignThe circuit design of the switched-line TTD phase shifter consists of choosing the line lengths, tailoring their bends to minimize reflections, and properly locating and impedance-matching the switches in the proximity of the T-junctions so as to maintain optimum return loss [24] across frequency even when one of the switches is in the open state and the effects of the corresponding open stub between it and the junction become manifest. Precedent for this type of design was set by Sokolov et al. [24], who positioned shunt FET switches at a distance of lg / 4 from either the input or output junction of a 1-bit 30-GHz switched-line phase shifter. In the case of the 4-bit RF MEMS?based TTD phase shifter under study, Kim et al. [23] adopted a similar approach by optimizing the performance of a representative single bit. In particular, they began by fabricating bit number 3 as a single-bit TTD circuit. The TTD lines consisted of 55 mm wide microstrip lines on a GaAs substrate with a thickness of 75 mm, and bends made up of appropriately chamfered 90° corners to minimize reflections. The switches utilized were Rockwell?s own metal-metal contact MEMS switches, like those described in Chapter 3 [25], utilizing 100 ´ 100-mm2 drive capacitors.
One deviation in the signal line width from the nominal 55-mm width was dictated by the separation between the drive capacitors, which was only 80 mm; thus, the signal line had to be narrowed down to 40 mm in a 300-mm section around the junctions. The high impedance implied by this line narrowing, however, was found via simulation to be virtually inconsequential to circuit performance up to a frequency of 40 GHz.
To match the open-stub transmission lines connected to the switches when in the open state, two avenues were pursued. First, in order to reduce the length of the open stub, the switch size was reduced. This resulted in an open stub with quarter-wavelength resonance frequency at 145 GHz (i.e., out of band). Second, to cancel the effective capacitance introduced by the open stub, an inductive line 16-mm-wide and 160-mm-long was introduced in series with the junctions.
While, in general, it would be expected for a reactive passive element, such as the series L, shunt (open stub) C two-port embodied by the junction, to worsen the delay flatness, Kim et al. [23] point out that it need not be so. Indeed, since the group delay of such a circuit is given by where C represents the open-stub capacitance and Z0 is a normalizing impedance, they indicate that the ripple resulting C as a result of the second-order zero in the denominator may be minimized by properly choosing L. The design approach was validated by the reported measurements .
Below 15 GHz, insertion/return loss performance of matched and unmatched circuits virtually coincides; however, beyond 15 GHz, the ripple in the return loss grows for the unmatched circuit from ~30 dB to ~10 dB, whereas for the matched circuit it remains at ~30 dB. Similarly, whereas the matched circuit exhibits less than 1-ps delay ripple up to 30 GHz, the ripple for the unmatched circuit reaches 5 ps just barely beyond 15 GHz.


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