UP/DOWN COUNTER

The down-counter is implemented by connecting the Q0 and Q1 outputs. Figure 29.1 F0F1 F2

digital logic design  UP/DOWN COUNTER

digital logic design  UP/DOWN COUNTER

The down-counter counter circuit is very similar to the up-counter circuit discussed earlier. The only change is the connection of the AND gate to the complementary outputs of the first and second flip-flops.

The up-counter and down-counter can be implemented as a single counter circuit by adding

some extra logic. In the circuit diagram, the Up-down counter is configured to count up or down by setting the UP/DOWNinput to logic 1 or 0 respectively. When the UP/DOWN input is set to logic 1, upper AND gates are enabled, allowing flip-flip 2 to toggle its state when F0 output of flip-flop 1 is logic 1. Similarly when both F0 and F1 outputs are logic 1, flip-flop 3

toggles its state. When theUP/DOWNinput is set to logic 0, the lower AND gates are

enabled. When F0 is logic 0, Q0 is logic 1 and the flip-flop 2 toggles its output state. Similarly,

when both outputs F0 and F1 are at logic 0, that is, Q0 and Q1 are at logic 1 the flip-flop 3

toggles its state. During the counting sequence, the UP/DOWNinput can be set to logic 1 or 0 at any time to reverse the counting sequence. Figure 29.2

digital logic design  UP/DOWN COUNTER

Figure 29.2a Up-Down Synchronous Counter

digital logic design  UP/DOWN COUNTER

Figure 29.2b Timing diagram of an Up-Down Synchronous Counter

Integrated Circuit Up/Down Decade Counter

Implementing a 4-bit Up/Down counter by connecting flip-flops and logic gates increases the circuit size and requires many connections. The 74HC190 is a 4-bit Up/Down Synchronous Counter available in an Integrated Circuit form. Figure 29.3. The counter has the following pins.

  1. Parallel data inputs D0, D1, D2 and D3
  2. Data outputs Q0, Q1, Q2 and Q3
  3. Positive edge-triggered CLOCK signal
  4. Active-low LOAD input which loads the 4-bit data applied at the counter inputs
  5. Active-low CTEN counter enable input
  6. D/U the count down/up input. When the input is set to logic 1, the counter counts down and when the input is set to logic 0, the counter counts up
  7. The MAX/MIN output that is set to high when the terminal count 1001 is reached when counting up or when the terminal count 0000 is reached when counting down. The MAX/MIN output is logic high for one complete cycle when a terminal count is reached.
  8. The Ripple Clock Output RCO goes low when the Counter reaches the terminal count 1001 or 0000 when counting up or down respectively. The RCO output remains low during the negative half of the clock cycle. The RCO, the MAX/MIN output along with CTEN input is used to cascade multiple counter ICs for implementing larger counters.

D0 D1 D2 D3

CTEN LOAD

MAX/MIN D/U 74HC190

RCO

CLK

Q0 Q1 Q2 Q3
Figure 29.3 74HC190 4-bit Synch rono us U p/Down Counter
Counter Decoding

In digital circuits the counter outputs are decoded using decoders or logic gates to determine when the counter is in a certain state in its counting sequence. For example, a 4-bit Modulus-16 counter counts from state 0 to state 15. A digital circuit is enabled when the count reaches count value 4, a second circuit is enabled when the count value reaches 8 and a third circuit is enabled when the count value reaches 12. A decoder using AND or NAND gates logic gates can be implemented. Figure 29.4

digital logic design  UP/DOWN COUNTER

Figure 29.4a Decoder circuit decoding counter outputs 4, 8 and 12

The output of the first AND gate is set to logic high when the counter output is set to 0100 (4). The output of the second AND gate is set to logic high when the counter output is set to 1000 (8). The NAND gate is set to logic low when the counter output is set to 1100 (12). The propagation delay due to ripple effect in Asynchronous counters, discussed earlier causes these Asynchronous counters to work erratically. The propagation problem also exists in Synchronous counters to some degree due to the propagation delays from the clock transition to the Q output of the flip-flop which varies slightly for each flip-flop. The timing diagram for the decoder circuit shows that the decoder outputs are activated for different time intervals at different intervals which are not in a proper sequence. Figure 29.4b. The counter output for count 2 is detected by the AND gate decoder during interval t2A to t3 and again for a very short interval at t4. Similarly, the counter output 8 is selected for a very short duration between intervals tAB and t9. The decoder outputs for very short durations at interval t2, t4, t6 and t8 are known as ‘gliches’.

Glitches can be eliminated by enabling the decoder outputs after the glitches have settled down. Glitches are removed by using the clock signal to enable the decoder circuit. Figure 29.5. The clock signal is connected to the inputs of each of the three decoder gates. During the second, positive half of the clock signal the three gates are enabled, all the glitches occur during the first negative half of the clock cycle during which the decoder gates are disabled. This method is known as Strobing method where the decoder outputs are activated after some delay allowing the glitches to settle down.

digital logic design  UP/DOWN COUNTER

Figure 29.4b Decoded Outputs of Synchronous Counter

digital logic design  UP/DOWN COUNTER

Glitches occur even with Integrated circuits due to different propagation delays between the clock transition and the variable path lengths between different inputs and outputs within the integrated circuit. The Glitches that occur at the output of a 74x 138 3-to-8 decoder connected to a 74HC163 counter can be removed by enabling the decoder during the second half of the clock signal. Figure 29.6

digital logic design  UP/DOWN COUNTER

digital logic design  UP/DOWN COUNTER

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