TIMING DIAGRAM OF A SYNCHRONOUS DECADE COUNTER


digital logic design  TIMING DIAGRAM OF A SYNCHRONOUS DECADE COUNTER

digital logic design  TIMING DIAGRAM OF A SYNCHRONOUS DECADE COUNTER

Mod-n Synchronous Counter

A Mod-n Synchronous can be implemented using appropriate number of J-K flip-flops connected together with their clocks triggered simultaneously. A synchronous counter which counts a truncated sequence of n unique states can be similarly implemented. The Modulus number represents the unique number of states which the counter counts in a sequence. The Modulus number determines the number of flip-flops required based on the relation n = 2m

where m is the number of flip-flops.

Integrated Circuit Synchronous Counters

Instead of connecting a large number of flip-flops together to form large Synchronous counters, counter circuits available in Integrated Circuit form can be quickly connected to form large counters. The 74HC163 is a 4-bit Synchronous Counter. Figure 28.2. The counter has the following pins.

  1. Parallel data inputs D0, D1, D2 and D3
  2. Data outputs Q0, Q1, Q2 and Q3
  3. Positive edge-triggered CLOCK signal
  4. Active-low CLR input which resets the Counter output to 0000
  5. Active-low LOAD input which loads the 4-bit data applied at the counter inputs
  6. Active-high ENT and ENP enable inputs. For the counter to operate both the enable inputs have to be high
  7. The Ripple Clock Output RCO goes high when the Counter reaches the terminal count 1111. The RCO output along with ENT and ENP enable input pins are used to cascade multiple counter ICs for implementing larger counters

D0 D1 D2 D3

CLR LOAD

RCO

ENT ENP CLK

Figure 28.2a 74HC163 4-bit Synchronous Counter

Referring to the timing diagram, the CLR signal is activated between interval t0 and t1.

The counter output is reset synchronously at interval t1 as the CLR signal is active at interval

t1. If the CLR signal is deactivated before interval t1 then the counter output is not reset. The

LOAD signal is activated between interval t1 and t2. At the clock transition at t2, the counter is loaded with the 4-bit data applied at the inputs D0, D1, D2 and D3. The ENP and ENT enable signals are activated before interval t3 and the counter increments to the higher count at clock transition at intervals t3 and t4. When the counter reaches the count 15 at interval t4, the RCO (Ripple Clock Output) is set to high indicating that terminal count has been reached. At intervals t5, t6, t7 and t8 the counter successively counts to 0, 1, 2 and 3. The counter enable signal ENP is deactivated after interval t8, which inhibits the counter from counting any further.

digital logic design  TIMING DIAGRAM OF A SYNCHRONOUS DECADE COUNTER

digital logic design  TIMING DIAGRAM OF A SYNCHRONOUS DECADE COUNTER

The 74HC160 is a 4-bit Synchronous Decade counter with the same input and output pins as the 74HC163. The RCO output of the decade counter is activated when the counter reaches its terminal count 1001.

Cascading Counters

It is very convenient to cascade Integrated Circuit counters together to form larger counters instead of connecting together flip-flops to implement a large counter. The enable inputs and Ripple Clock Outputs of the Integrated Circuit counters allow cascading of multiple counters together. Two, 74HC160 decade counters are shown connected together to divide the input frequency by 10 and 100. Figure 28.3. The 74HC163 can also be similarly cascaded together.

digital logic design  TIMING DIAGRAM OF A SYNCHRONOUS DECADE COUNTER

CLR LOAD

digital logic design  TIMING DIAGRAM OF A SYNCHRONOUS DECADE COUNTER

digital logic design  TIMING DIAGRAM OF A SYNCHRONOUS DECADE COUNTER

Figure 28.3b Timing diagram of a Cascaded Decade Counter

In the timing diagram, at interval t9 the first decade counter reaches the terminal count 1001. The RCO output of the counter is set to logic 1. The RCO of the first counter is connected to the ENP and ENT enable pins of the second counter, therefore the counter is enabled. At interval t10 on a positive clock transition the first counter increments to count 0000. Since the second counter is also enabled, it is incremented to 0001. As soon as the first counter is incremented to 0000, the ECO signal is deactivated which in-turn also inhibits the second counter. The first counter counts from 0001 to 1000 in the intervals t11 to t19. At interval t19 the first counter again reaches its terminal count 1001, the RCO output of counter once again becomes active thereby activating the second counter. At interval t20 on a positive clock transition the first and second counters increment to count 0000 and 0010 respectively. The RCO signal is again deactivated inhibiting the second counter from counting. This sequence continues after the first counter reaches its terminal count.

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