Integrated Circuit Counters with Truncated Sequences
Earlier, a decade counter was implemented by truncating the counting sequence of a MOD-16 counter. The Integrated Circuit Counters can also be configured as MOD-n counters where n represents the truncated sequence and is less than 16. Figure 28.4 shows the circuit diagram of the 74HC163 counter configured as Mod-7 counter. The counter is preset with the count value 1001 by setting the LOAD/NORMAL input to logic 1 at the NOR gate input. At the positive clock transition t1, the count value is loaded. The counter increments and at interval t7
it reaches the terminal count. The RCO output is set to logic 1 which sets the LOAD input to logic 0. At the positive clock transition at interval t8 the preset value 1001 is reloaded and the counter continues its counting sequence.
D0 D1 D2 D3 LOAD/NORMAL 1/0
Figure 28.4a 74HC163 configured as Mod-7 counter Figure 28.4b The timing diagram of a truncated Mod-7 Counter
Another method to configure an Integrated Circuit counter is to reset the counter when it reaches the maximum count value of its truncated sequence. This requires extra logic in the form of logic gates that determine the terminating state and reset the counter. The circuit diagram of the counter is shown. Figure 28.5
D0 D1 D2 D3LOAD/NORMAL 1/0
Figure 28.5a 74HC161 configured as Mod-9 counter
Q0 Q1 Q2 Q3
The counter used is 74HC161 instead of 74HC163. The 74HC161 has an Asynchronous Clear input, where as the 74HC163 counter has a synchronous Clear input. At time interval t9 the counter increments to 1001 which sets the output of the AND gate to logic
1. The NOR gate output is set to logic low which activates the clear input and resets the counter to 0000. The 74HC163 counter which has a synchronous clear input, will reset counter resets at interval t10 when there is a transition at the clock input. It is clear from the timing diagram that to implement a Mod-9 counter the 74HC161 instead of 74HC163 counter has to be used.
Cascaded Counters with Truncated Sequences
Cascaded counters can also be configured to count in a truncated sequence. The circuit diagram of three cascaded 74HC163 is shown. Figure 28.6. The 12-bit cascaded counter is loaded with initial count value 1000 0000 0000. When the counter counts to 1111 1111 1111, the RCO output set to logic 1 by the third counter reloads the initial count values 0000, 0000 and 1000 in all the three counters respectively. The 12-bit counter can be configured for maximum count sequence as Modulus 4096 counter. The counter has been configured to count from 1000 0000 0000 to 1111 1111 1111 that is 2048 states or Modulus 2048 counter.
An up-down counter can increment its output count value at each clock transition or decrement its count value at each clock transition, depending upon the count mode it is configured in. The counter can be reconfigured to count in the opposite direction during its count sequence. The circuit of an up-down 3-bit counter can be developed by studying the up-down count sequence of the counter. Table 28.1.
Table 28.1a Up-counting sequence of a 3-bit Synchronous Counter
Table 28.1b Down-counting sequence of a 3-bit Synchronous Counter A 3-bit Synchronous up-counter has been discussed earlier. Consider the implementation of down-counter, the up and down counter can be combined to form a single configurable up- down counter. For the down-counting sequence the output Q0 of the first flip-flop toggles
between 0 and 1, therefore the J-K inputs are connected to logic 1. The output Q1 of the second flip-flop toggles between logic 0 and 1 when the Q0 output is logic 0 orQ0 is logic 1. The output Q2 of the third flip-flop toggles when Q0 and Q1 outputs are both logic 0 or Q0 and Q1 are both logic 1.