Counter Applications

1. Digital Clock

digital logic design  Counter Applications

The primary use of counter is in counting applications and sequencing through a set of operations. A digital clock can be implemented using the AC 50 Hz frequency as the clock signal. Figure 29.8

In the digital clock circuit the 50 Hz, 220 volt ac mains sinusoidal signal is shaped into a 50 Hz, 5 volt square-wave signal. A divide-by-50 counter divides the input 50 Hz signal to a 1 Hz signal. The Seconds, divide-by-60 counter counts up to sixty seconds (0 to 59). The Minutes, divide-by-60 counter also counts up to sixty minutes (0-59). The Hours, decade counter counts from 0 to 9. The flip-flop connected to the output of the decade counter is set to 0 or 1 to represent hours from 0 to 9 and 10 to 12 respectively.

digital logic design  Counter Applications

The circuit diagram of the Divide by 60 Seconds and Minutes counter is shown in figure

29.9. The 74HC160A decade counter is sued which has Asynchronous clear. The divide by 60 counter is implemented by cascading two 74HC160A counters. The least significant counter which is the units counter is configured as a decade counter and counts from 0000 to 1001. On reaching the terminal count value, the RCO output of the Units counter is set to high which enables the tens counter. The tens counter is configured as a Mod-6 counter, thus it counts from 000 to 101. The NAND gate output is set to low when the counter counts up to 110, the NAND gate output is connected to the asynchronous clear input which resets the counter to

000. When the tens counter reaches its terminal count 101, and the units counter reaches its terminal count 1001, the AND gate output is set to logic high to indicate the terminal count 59 of the divide by 60 counter. The output of the AND gate is connected to the counter enable pins ENT and ENP of the next stage, thus on reaching the terminal count the next stage is enabled and the count is incremented by 1 on a clock transition.

The hours counter is implemented using a single decade counter and a flip-flop. Two counters are not required as the hours counter counts 12 unique output states. Implementation of a Mod-12 requires 5 flip-flops. Figure 29.10

digital logic design  Counter Applications

digital logic design  Counter Applications

The hours unit counter circuit is configured as a decade counter, counting from 0000 to 1001 when it is enabled by the Minutes counter circuit. The terminal count 1001 is detected by the NAND gate (1) which sets the J input of the flip-flop to logic 1. The K input of the flip-flop is at Logic 0, therefore on a clock transition the J–K flip-flop output is set to logic 1 when the units counter recycles to 0000. The NOT gate connected to the clock input of the J-K flip-flop allows the J-K flip-flop to trigger when the units counter is triggered to count from 1001 to 0000. The unit counter counts to 0001 and 0010 to represent hours 11 and 12 respectively along with the output of the J-K flip-flop which is set to logic 1. On the next clock transition when the units counter counts to 0011 the NAND gate (2) output set to logic 0 reloads the units counter with the count value 0001 and the J-K flip-flop toggles to 0 output as its K input which is set to logic

1.

digital logic design  Counter Applications

Figure 29.10b Hours Counter timing diagram

2. Frequency Counter

A frequency counter is used to measure the frequency of an input signal. The basis for the operation of a frequency counter is counting of the clock pulses in predetermined time interval. The frequency of periodic signal is the number of cycles in a time period of one second. The frequency of the unknown signal can be calculated by counting the number of clock pulses of the unknown signal and dividing the count number by the time interval in which the clock pulses are counted, Figure 29.11

In the circuit shown, the input signal with unknown frequency is applied at the AND gate input. The second input of the AND gate is connected to a signal which determines the sampling interval. The signal is set to logic high at interval t1 to enable the AND gate allowing the input signal to be connected to the clock input of the counter circuit. The sampling interval signal is set to logic low at the end of the sampling interval t2 to disable the AND gate and inhibit the counter from counting. Before the counter counts the clock pulses of the input signal it is reset by activating the Asynchronous input to clear the counter at interval t0. At the end of the sampling interval the counter output is displayed on 7-segment displays.

digital logic design  Counter Applications

BCD & Segment Interval Decoder

digital logic design  Counter Applications

Figure 29.11a Frequency Counter Circuit

digital logic design  Counter Applications

Figure 29.11b Timing diagram of the Frequency Counter Circuit

The accuracy of the frequency counter depends on the duration of the timing sampling interval, which must be very accurate. Consider that during a sampling interval of 1 second 4573 clock pulses of the input signal are measured. Thus, the frequency of the unknown signal is 4573 Hz. If the same input signal is sampled using a 0.1 second sampling interval then

457.3 pulses are counted, which means that either 457 or 458 will be counted depending on the start of the sampling interval at t1. Similarly, if the sampling interval is reduced to 0.01 seconds, the numbers of clock pulses measured are 45.73, which means that either 45 or 46 will be read.

Very accurate sampling intervals are implemented using cascaded counter which is connected to a very accurate timing signal generated by a crystal controlled oscillator (Astable multi-vibrator). The output timing signal of each cascade section is available at a switch which is used to select the appropriate timing signal for controlling the sampling interval. The output of the switch is connected to the clock input of a negative triggered J-K flip-flop, which divides the input signal by 2. Thus, when the 1 Hz sampling interval is selected, the signal at the output of the J-K flip-flop has a time period of 2 seconds. Figure 29.12

100 100

digital logic design  Counter Applications

The detailed circuit diagram and the timing diagram of the frequency diagram are shown in figure 29.13. In the timing diagram the Sampling Interval pulse is obtained from the output of the J-K flip-flop shown in figure 29.8. The duration of the Sampling interval pulse can be selected through the switch. The sampling interval signal is connected to the input of the 3input AND gate and the clock input of the second J-K flip-flop which toggles its output at each negative transition of the clock. When the output of the second flip-flop changes to logic 1 (interval t1) it triggers the One-Shot which generates a short output pulse which clears the Counter circuit. At interval t2 during the positive half of the sampling interval when the output of the second J-K flip-flop is high the 3-input AND gate is enabled and the input signal with unknown frequency is applied at the input of the counter, which count the input signal pulses. At interval t3 there is negative transition of the sampling signal, which triggers the second flip-flop changing its output to logic 0. Logic 0 output of the flip-flop disables the 3-input AND gate inhibiting the counter from counting. The pulses counted by the counter during interval t2 to t3 are directly displayed.

Input Signal with

digital logic design  Counter Applications

Figure 29.13a Detailed circuit diagram of a frequency counter

digital logic design  Counter Applications

t0 t1 t2 t3 t4 t5 t6t7t8t9

Figure 29.13b Timing diagram of the frequency counter circuit

Design of Synchronous Counters

The counters that have been discussed are binary counters that count in a sequence either upwards or downwards. The count start and end sequence of a counter can also be set arbitrarily and the counter can then count up or down with in the terminal count limits. Counters can also be designed that do not count in a sequence, instead they sequence through a set of predefined arbitrary values. Counters can also be implemented using D flip-flops instead of J-K flip-flops. Counters are sequential circuits which are designed using standard set of steps.

Sequential Circuit (State Machine)

A general Sequential circuit consists of a combinational circuit and a memory circuit (flip-flop). In a clocked Sequential circuit the memory element has a clock input. At any given instant the memory element is in its present state. On a clock transition the output of the memory element changes to the next state. The next state is determined by the inputs applied at the memory input at the time of clock transition. The inputs to the memory which allow the memory to change its state on a clock transition are known as excitation inputs or excitation variables. The present state of the memory is represented by state variables. The state variables and the inputs to the sequential circuit determine the sequential circuit output. Figure

29.14

digital logic design  Counter Applications

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